Most sensing devices such as temperature, pressure, level or flow rate sensors yield signals which are analog in nature. Usually, these analog signals are continuous over some normally predetermined range. In order to use digital computing devices to process these signals, they must be transformed to digital or discrete signals. This process is known as analog-to-digital conversion and the circuits or devices used to perform this conversion are called A/D converters. Digital computers, particularly microcomputers, on account of their flexibility, programmability, and accuracy are now emerging as a desirable solution to many control problems. In many applications, it is either highly desirable or necessary to perform A/D conversion very quickly, and to present the digital output signals in parallel form to a bus or other multiple conductor data highway connected to a digital computer. Such applications include automobile engine, brake and transmission control systems, image processing, process control, radar, data acquisition and logging, and the like.
There are several parallel A/D converter structures which have been proposed, and a few are currently being used commercially. Each structure possesses certain advantages and disadvantages with respect to speed (that is, conversion time), precision, power consumption, cost, number of bits achievable by the state of the art, and the like. One widely used structure is a parallel A/D converter which requires 2.sup.N -1 or more comparators in the circuit to achieve an N-bit converter. Thus, to realize an 8-bit converter requires 255 or more comparators. Examples of such converters are shown in the following four U.S. patents:
______________________________________ U.S. Pat. No. Inventor(s) ______________________________________ 3,611,350 Leibowitz 3,829,853 Freedman 4,596,978 Fujita 4,600,916 Masuda et al. ______________________________________
This now-conventional style of converter requires far more than N comparators to produce an N-bit A/D conversion, and requires many other accurate components as well. Due to the formidable practical difficulties associated with implementing large amounts of precision circuitry and many comparators, the use of such parallel converters to achieve A/D conversion for large N is still very limited. Expense considerations and the upper limit on how many components can be practically integrated in a single integrated circuit (IC) chip also limit the use and maximum precision of such converters.
Another well-known approach to analog-to-digital conversion is the successive approximation technique of which the A/D converter shown in U.S. Pat. No. 4,649,371 to Kolluri is an example. The structure disclosed therein operates synchronously and requires at least N clock cycles to complete a conversion, and in addition also requires electronic hardware such as one or more registers. An additional explanation of this technique and other A/D techniques is Provided in G.B. Clayton, "Analog to Digital Conversion Techniques", DATA CONVERTERS, Chap. 3, pp. 40-79 (John Wiley & Sons, N.Y., 1982).
Several designs have been proposed for parallel A/D converters using N or 2N comparators. The following five patents uncovered during a preliminary patent search disclose such parallel A/D converter structures:
______________________________________ U.S. Pat. No. Inventor(s) ______________________________________ 4,275,386 Michel et al. 4,608,555 Hoeft 4,660,166 Hopfield 4,718,591 Hopfield et al. 4,769,628 Hellerman ______________________________________
The Michel et al patent, the Hoeft patent and the Hellerman patent each disclose the concept of using an asynchronous parallel A/D converter which has only N comparators. Each of the disclosed converters may be said to utilize a modified successive approximation technique wherein the value of the highest order digit of the analog input signal is discerned first, followed by the discernment of the next most significant bit and so on, on down to the unit bit. The converters in the Michel et al patent and the Hoeft patent require the use of precision current sources. The Michel et al converter also requires the use of a two-position switch with each comparator and voltage reference values provided by a diode network or the like. The converter in the Hoeft patent also requires the use of N current dividers, a voltage-to-current converter and current splitter. The converter in the Hellerman patent also requires the use of a solid-state switch with each comparator. These additional components add to the complexity of and limit the number of bits of resolution of these designs.
Another approach to parallel A/D converters is provided in U.S. Pat. Nos. 4,660,166 to J.J. Hopfield and U.S. Pat. No. 4,719.591 to J.J. Hopfield and D.W. Tank, and in the following two journal articles: D.W. Tank and J.J. Hopfield, "Simple Neural Optimization Networks: An A/D Converter, Signal Decision Circuit, and a Linear Programming Circuit", IEEE Transactions of Circuits and Systems, Vol CAS-33, No. 5, pp. 533-541 (May, 1986), and J.J. Hopfield and D.W. Tank, "Computing With Neural Circuits: A Model" Science. Vol. 233, pp. 625-633 (Aug. 8, 1986). The A/D converter designs disclosed in these references by Hopfield and/or Tank are somewhat similar in topography to that of the converters of the present invention. However, as is noted in first journal article, their A/D converter is unable to guarantee an accurate result for all analog input values, unless the input signal to the converter is momentarily reset to zero before the circuit is put to work.
The foregoing problem with the Hopfield A/D converter is also noted in another reference, namely B. Lee and B. Sheu, "An Investigation of Local Minima of Hopfield Networks for Optimization Circuits", Proceedings of the 1988 IEEE Int'l. Conf. On Neural Networks, pp. 1-45 to 1-51 (San Diego, Calif., July 24-27, 1988). These authors propose an add-on circuit to eliminate the localized conditions or traps that the Hopfield A/D converter can get into. However, add-on circuitry further increases the number of comparators required and the overall complexity of the circuitry and interconnections.
In light of the foregoing comments, it is clear that there still remains a need for a simple, low cost and reliable parallel A/D converter capable of operating at high speeds and with high precision, that is with many bits. In particular, there is a need for such an A/D converter which requires relatively few components, is inexpensive and which does not require precision current sources, solid-state switches or other complicated components for the A/D conversion process that tend to limit the ultimate accuracy or expandability of an A/D converter.
Therefore, it is a principal object of the present invention to provide a N-bit asynchronous high-speed parallel A/D converter including only N comparators and having minimal structural complexity and maximum reliability.
It is a related object of the invention to provide an A/D converter which uses few components especially a minimum number of active components, is very economical to produce, draws a minimum amount of power, is very reliable and is easy to manufacture using integrated circuit technology.
It is another object of the present invention to provide an A/D converter design which can be readily expanded, on account of minimum number of components and its design simplicity, to a greater number of bits in the digital output than is practical using well-known conventional A/D converter designs.
It is further an object of the present invention to provide a parallel A/D converter design which can be used to handle either unipolar or bipolar analog input signals.